Semiconductor memory devices
US11195836B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 2, 2020 |
| Grant date | Dec 7, 2021 |
| Priority date | — |
| Expiry date | May 8, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/43
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A semiconductor memory device includes a stack structure having a plurality of layers vertically stacked on a substrate, each layer including, a first bit line and a gate line extending in a first direction, a first semiconductor pattern extending in a second direction between the first bit line and the gate line, the second direction intersecting the first direction, and a second semiconductor pattern adjacent to the gate line across a first gate insulating layer, the second semiconductor pattern extending in the first direction, a first word line adjacent to the first semiconductor pattern and vertically extending in a third direction from the substrate, a second bit line connected to an end of the second semiconductor pattern and vertically extending in the third direction from the substrate, and a second word line connected to another end of the second semiconductor pattern and vertically extending in the third direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.