Method of fabricating a semiconductor device having reduced contact resistance

US11195923B2 · kind B2 · utility

Assignee

• Applied Materials, Inc. · US

Inventors

• Gaurav Thareja · Santa Clara, US
• Xuebin Li · Santa Clara, US
• Abhishek Dube · Fishkill, US
• Yi-Chiau Huang · Fremont, US
• Tushar Mandrekar · Santa Clara, US
• Andy Lo · San Diego, US
• Patricia M. Liu · Saratoga, US
• Sanjay Natarajan · Portland, US
• Saurabh Chopra · Sunnyvale, US

Key dates

• Filing date: Nov 8, 2019
• Grant date: Dec 7, 2021
• Expiry date: Dec 12, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/62
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Implementations of the present disclosure generally relate to methods for forming a transistor. More specifically, implementations described herein generally relate to methods for forming a source/drain contact. In one implementation, the method includes forming a trench in a dielectric material to expose a source/drain region of a transistor, performing a pre-clean process on the exposed source/drain region, forming a doped semiconductor layer on the source/drain region by an epitaxial deposition process, and fill the trench with a conductor. The doped semiconductor layer has a lower electrical resistance than the source/drain region due to a higher dopant concentration in the doped semiconductor layer. As a result, the contact resistance of the source/drain contact is reduced.