High resolution analog to digital converter with factoring and background clock calibration
US11196438B1 · kind B1 · utility
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20Claims
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Key dates
| Filing date | Jan 22, 2021 |
| Grant date | Dec 7, 2021 |
| Priority date | — |
| Expiry date | Jan 22, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/46
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Described are apparatus and methods for analog to digital converter (ADC) with factoring and background clock calibration. An apparatus includes an ADC configured to sample and convert differential input signals using a reference clock to obtain a defined number of samples during a first state in an acquisition clock cycle, and a finite state machine circuit configured to obtain the defined number of samples from the ADC using a clock based on the reference clock, factor the defined number of samples based on at least a common mode offset associated with the ADC, and send offset factored output to a controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.