Methods and systems for inter-pipeline data hazard avoidance
US11200064B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 14, 2020 |
| Grant date | Dec 14, 2021 |
| Priority date | — |
| Expiry date | Oct 14, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3889
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and parallel processing units for avoiding inter-pipeline data hazards wherein inter-pipeline data hazards are identified at compile time. For each identified inter-pipeline data hazard the primary instruction and secondary instruction(s) thereof are identified as such and are linked by a counter which is used to track that inter-pipeline data hazard. Then when a primary instruction is output by the instruction decoder for execution the value of the counter associated therewith is adjusted (e.g. incremented) to indicate that there is hazard related to the primary instruction, and when primary instruction has been resolved by one of multiple parallel processing pipelines the value of the counter associated therewith is adjusted (e.g. decremented) to indicate that the hazard related to the primary instruction has been resolved. When a secondary instruction is output by the decoder for execution, the secondary instruction is stalled in a queue associated with the appropriate instruction pipeline if at least one counter associated with the primary instructions from which it depends indicates that there is a hazard related to the primary instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.