Multiplier and operation method based on 1T1R memory
US11200949B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 12, 2019 |
| Grant date | Dec 14, 2021 |
| Priority date | — |
| Expiry date | Jul 12, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/82
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention discloses a multiplier and an operation method based on 1T1R memory. The multiplier includes: a 1T1R crossbar A1, a 1T1R crossbar A2, a 1T1R crossbar A3, and a peripheral circuit. The 1T1R matrices are configured to realize operation and store result of it, and the peripheral circuit is configured to transfer data and control signals, thereby controlling the operation and storage process of the 1T1R matrices. An operation circuit is configured to respectively achieve NOR Boolean logic operations, two-bit binary multipliers, and optimization. The operation method corresponding to the operation circuit respectively completes the corresponding calculation and storage process by controlling an initialization resistance state of 1T1R devices, the size of a word line input signal, the size of a bit line input signal, and the size of a source line input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.