Nanowire stack GAA device and methods for producing the same
US11201243B2 · kind B2 · utility
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10References
18Claims
0Family size
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Key dates
| Filing date | Sep 3, 2019 |
| Grant date | Dec 14, 2021 |
| Priority date | — |
| Expiry date | Sep 3, 2039 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S977/938
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
The current disclosure describes techniques for forming a gate-all-around device where semiconductor layers are released by etching out the buffer layers that are vertically stacked between semiconductor layers in an alternating manner. The buffer layers stacked at different vertical levels include different material compositions, which bring about different etch rates with respect to an etchant that is used to remove at least partially the buffer layers to release the semiconductor layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.