Error correcting memory systems
US11204835B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 11, 2019 |
| Grant date | Dec 21, 2021 |
| Priority date | — |
| Expiry date | Oct 11, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/19
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Error correcting memory systems and methods of operating the memory systems are disclosed. In some embodiments, a memory system includes: a data memory; an ECC memory; and a data scrubbing circuit electrically coupled to the ECC memory and the data memory. The data scrubbing circuit may be configured to, in response to receiving a scrub data command, correct an error in the data memory. A code word length used to correct the error may be longer than a word length used during normal access of the data memory. In some embodiments, a memory system includes a first memory circuit associated with a first bit error rate and a second memory circuit associated with a second bit error rate. In some embodiments, a memory system includes an error correctable multi-level cell (MLC) array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.