Patent · US Active

Scalable sparse matrix multiply acceleration using systolic arrays with feedback inputs

US11204977B2 · kind B2 · utility

4Cited by

4References

20Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Subramaniam Maiyuran · Citrus, US
Jorge Parra · Cameron Park, US
Supratim Pal · Bengaluru, IN
Ashutosh Garg · Sunnyvale, US
Shubra Marwaha · Folsom, US
Chandra Gurram · Folsom, US
Darin Starkey · Roseville, US
Durgesh Borkar · Folsom, US
Varghese George · Folsom, US

Key dates

Filing date	Jun 26, 2020
Grant date	Dec 21, 2021
Priority date	—
Expiry date	Jun 26, 2040

Classification

Technology area (CPC G)Physics
CPC primaryG06F15/8046
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Described herein is an accelerator device including a host interface, a fabric interconnect coupled with the host interface, and one or more hardware tiles coupled with the fabric interconnect, the one or more hardware tiles including sparse matrix multiply acceleration hardware including a systolic array with feedback inputs.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.