Memory device and a method for forming the memory device
US11205478B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 1, 2019 |
| Grant date | Dec 21, 2021 |
| Priority date | — |
| Expiry date | Jul 11, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/82
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device may include a substrate having conductivity regions and a channel region. A first voltage line may be arranged over the channel region. Second, third, and fourth voltage lines may each be electrically coupled to a conductivity region. Resistive units may be arranged between the third voltage line and the conductivity region electrically coupled to the third voltage line, and between the fourth voltage line and the conductivity region electrically coupled to the fourth voltage line. A resistance adjusting element may have at least a portion arranged between one of the resistive units and one of the conductivity regions. An amount of the resistance adjusting element between the first resistive unit and the conductivity region electrically coupled to the third voltage line may be different from that between the second resistive unit and the conductivity region electrically coupled to the fourth voltage line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.