Error detection and correction using machine learning
US11205498B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 8, 2020 |
| Grant date | Dec 21, 2021 |
| Priority date | — |
| Expiry date | Jul 8, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6325
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system including a memory device and a memory controller including a processor. The memory controller is configured to read outputs from the memory cells in response to a read command from a host and to convert the read outputs to a first codeword. The processor performs a first error correcting code (ECC) operation on the first codeword. The processor is further configured to apply, for each selected memory cell among the memory cells, a corresponding one of the read outputs and at least one related feature as input features to a machine learning algorithm to generate a second codeword, and the memory controller is configured to perform a second ECC operation on the second codeword, when the first ECC operation fails.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.