Semiconductor package including a thermal conductive layer and method of manufacturing the same
US11205604B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 1, 2018 |
| Grant date | Dec 21, 2021 |
| Priority date | — |
| Expiry date | Oct 24, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a semiconductor chip having a first surface that is an active surface and a second surface opposing the first surface, a first redistribution portion disposed on the first surface, the first redistribution portion including a lower wiring layer electrically connected to the semiconductor chip, a thermal conductive layer disposed on the second surface of the semiconductor chip, a sealing layer surrounding a side surface of the semiconductor chip and a side surface of the thermal conductive layer, and a second redistribution portion disposed on the sealing layer, the second redistribution portion including a first upper wiring layer connected to the thermal conductive layer, the second redistribution portion including a second upper wiring layer electrically connected to the semiconductor chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.