Semiconductor package including multiple semiconductor chips
US11205631B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 18, 2020 |
| Grant date | Dec 21, 2021 |
| Priority date | — |
| Expiry date | Mar 18, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1431
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided is a semiconductor package including a package structure including a base connection member including a redistribution layer, a first semiconductor chip including a plurality of first connection pads connected to the redistribution layer, an encapsulant disposed on the base connection member and covering at least a portion of the first semiconductor chip, and a backside connection member disposed on the encapsulant and including a backside wiring layer electrically connected to the redistribution layer, and a second semiconductor chip disposed on the base connection member or the backside connection member, the second semiconductor chip including a plurality of second connection pads connected to the redistribution layer or the backside wiring layer, the second semiconductor chip including a logic circuit, the first semiconductor chip including a logic input and output terminals that are connected to the logic circuit through at least one of the redistribution layer and the backside wiring layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.