Methods for reducing defects in semiconductor plug in three-dimensional memory device

US11205662B2 · kind B2 · utility

Assignee

• YANGTZE MEMORY TECHNOLOGIES CO., LTD. · CN

Inventors

• Fandong Liu · 红钢城街道, CN
• Wenyu Hua · Hubei, CN
• Jia He · Yangshuo, CN
• Linchen Wu · 红钢城街道, CN
• Yue Qiang Pu · 红钢城街道, CN
• Zhiliang Xia · 红钢城街道, CN

Key dates

• Filing date: Aug 14, 2020
• Grant date: Dec 21, 2021
• Expiry date: Aug 14, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/02189
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Embodiments of 3D memory devices with a dielectric etch stop layer and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. The method includes forming a dielectric etch stop layer. The dielectric etch stop is disposed on a substrate. The method also includes forming a dielectric stack on the dielectric etch stop layer. The dielectric stack includes a plurality of interleaved dielectric layers and sacrificial layers. The method further includes forming an opening extending vertically through the dielectric stack and extending the opening through the dielectric etch stop layer. In addition, the method includes forming a selective epitaxial growth (SEG) plug at a lower portion of the opening. The SEG plug is disposed on the substrate. Moreover, the method includes forming a channel structure above and in contact with the SEG plug in the opening. The method further includes forming a memory stack comprising a plurality of interleaved dielectric layers and conductor layers by replacing the sacrificial layers in the dielectric stack with the conductor layers.