Embedded MRAM device with top via
US11205678B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 3, 2020 |
| Grant date | Dec 21, 2021 |
| Priority date | — |
| Expiry date | May 10, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/80
Abstract
Techniques for integrating an embedded MRAM device with a BEOL interconnect structure are provided. In one aspect, a method of forming an embedded MRAM device includes: depositing a cap layer onto a substrate; forming a metal line and metal pad on the cap layer; patterning the metal line to form first top vias, and the metal pad to form a second top via; depositing a dielectric material onto the substrate surrounding the first/second top vias; recessing the second top via to form a bottom contact via self-aligned to the metal pad which serves as a bottom contact; forming an MRAM cell over the bottom contact via; and forming first/second top contacts in contact with the first top vias/the MRAM cell. An embedded MRAM device is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.