Metal gate structure and method of fabricating the same
US11205705B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 29, 2018 |
| Grant date | Dec 21, 2021 |
| Priority date | — |
| Expiry date | Feb 1, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/014
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A gate structure includes a substrate divided into an N-type transistor region and a P-type transistor region. An interlayer dielectric covers the substrate. A first trench is embedded in the interlayer dielectric within the N-type transistor region. A first gate electrode having a bullet-shaped profile is disposed in the first trench. A gate dielectric contacts the first trench. An N-type work function layer is disposed between the gate dielectric layer and the first gate electrode. A second trench is embedded in the interlayer dielectric within the P-type transistor region. A second gate electrode having a first mushroom-shaped profile is disposed in the second trench. The gate dielectric layer contacts the second trench. The N-type work function layer is disposed between the gate dielectric layer and the second gate electrode. A first P-type work function layer is disposed between the gate dielectric layer and the N-type work function layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.