Dual self-aligned gate endcap (SAGE) architectures

US11205708B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Sairam Subramanian · Dallas, US
• Walid M. Hafez · Portland, US
• Sridhar Govindaraju · Hillsboro, US
• Mark Liu · West Linn, US
• Szuya S. Liao · Portland, US
• Chia-Hong Jan · Portland, US
• Nick Lindert · Beaverton, US
• Christopher KENYON · Portland, US

Key dates

• Filing date: Apr 2, 2018
• Grant date: Dec 21, 2021
• Expiry date: Apr 21, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/8314
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Dual self-aligned gate endcap (SAGE) architectures, and methods of fabricating dual self-aligned gate endcap (SAGE) architectures, are described. In an example, an integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin is parallel with the first semiconductor fin. A first gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. A second gate endcap isolation structure is in a location of the cut along the length of the first semiconductor fin.