Inventor · West Linn, OR, US

Mark Liu

51Patents
10h-index
54Co-inventors
81Inventor score

Filing activity: Aug 10, 2000 → Nov 6, 2023

Most-cited inventions

PatentTitleAreaCited byStatus
US7456068B2 Forming ultra-shallow junctions Electricity 51 Active
US7052978B2 Arrangements incorporating laser-induced cleaving Performing Operations; Transporting 49 Expired
US8901537B2 Transistors with high concentration of boron doped germanium Electricity 47 Active
US6590271B2 Extension of shallow trench isolation by ion implantation Electricity 29 Expired
US6432798B1 Extension of shallow trench isolation by ion implantation Electricity 25 Expired
US7211501B2 Method and apparatus for laser annealing Emerging Cross-Sectional Technologies 23 Expired
US7663192B2 CMOS device and method of manufacturing same Electricity 23 Active
US8896030B2 Integrated circuits with selective gate electrode recess Electricity 19 Active
US9627384B2 Transistors with high concentration of boron doped germanium Electricity 12 Active
US6675057B2 Integrated circuit annealing methods and apparatus Electricity 12 Expired
US7741230B2 Highly-selective metal etchants Electricity 9 Active
US9443980B2 Pulsed laser anneal process for transistors with partial melt of a raised source-drain Electricity 6 Active
US7115479B2 Sacrificial annealing layer for a semiconductor device and a method of fabrication Electricity 5 Expired
US6936518B2 Creating shallow junction transistors Electricity 4 Expired
US8779477B2 Enhanced dislocation stress transistor Electricity 4 Active
US9418898B2 Integrated circuits with selective gate electrode recess Electricity 4 Active
US10020232B2 Integrated circuits with recessed gate electrodes Electricity 3 Active
US11570405B2 Systems and methods for facilitating external control of user-controlled avatars in a virtual environment in order to trigger livestream communications between users Electricity 3 Active
US10170314B2 Pulsed laser anneal process for transistor with partial melt of a raised source-drain Electricity 2 Active
US7439571B2 Method for fabricating metal gate structures Electricity 2 Expired
US11217582B2 Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls Electricity 2 Active
US11387320B2 Transistors with high concentration of germanium Electricity 2 Active
US10651093B2 Integrated circuits with recessed gate electrodes Electricity 2 Active
US11750774B2 Systems and methods for triggering livestream communications between users based on proximity-based criteria for avatars within virtual environments that correspond to the users Electricity 1 Active
US9006069B2 Pulsed laser anneal process for transistors with partial melt of a raised source-drain Electricity 1 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.