Addressing for disaggregated memory pool
US11210218B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 3, 2020 |
| Grant date | Dec 28, 2021 |
| Priority date | — |
| Expiry date | Sep 3, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/163
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for memory address mapping in a disaggregated memory system includes receiving an indication of one or more ranges of host physical addresses (HPAs) from a compute node of a plurality of compute nodes, the one or more ranges of HPAs including a plurality of memory addresses corresponding to different allocation slices of the disaggregated memory pool that are allocated to the compute node. The one or more ranges of HPAs are converted into a contiguous range of device physical addresses (DPAs). For each DPA, a target address decoder (TAD) is identified based on a slice identifier and a slice-to-TAD index. Each DPA is mapped to a media-specific physical element of a physical memory unit of the disaggregated memory pool based on the TAD.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.