Reconfiguring layout and sizing for transistor components to simultaneously optimize logic devices and non-logic devices
US11210447B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 16, 2019 |
| Grant date | Dec 28, 2021 |
| Priority date | — |
| Expiry date | Jul 7, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6219
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The first type of semiconductor device includes a first fin structure extending in a first direction, a first gate, and a first slot contact disposed over the first fin structure. The first gate extends in a second direction and has a first gate dimension measured in the first direction. The first slot contact has a first slot contact dimension measured in the first direction. A second type of semiconductor device includes: a second fin structure extending in a third direction, a second gate, and a second slot contact disposed over the second fin structure. The second gate extends in a fourth direction and has a second gate dimension measured in the third direction. The second slot contact has a second slot contact dimension measured in the third direction. The second slot contact dimension is greater than the second gate dimension and greater than the first slot contact dimension.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.