Ferroelectric memory device
US11211108B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 19, 2018 |
| Grant date | Dec 28, 2021 |
| Priority date | — |
| Expiry date | Dec 19, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B53/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The disclosed technology generally relates to a memory device, and more particularly to a ferroelectric memory device and a method of operating the memory device. According to one aspect, a memory device comprises a bit cell. The bit cell comprises a write transistor, a read transistor and a ferroelectric capacitor. A write word line is connected to a gate terminal of the write transistor. A write bit line is connected to a first terminal of the write transistor. A read bit line connected to a terminal of the read transistor. A first control line is connected to a first electrode of the ferroelectric capacitor. A second terminal of the write transistor is connected to the gate terminal of the read transistor, and a second electrode of the ferroelectric capacitor is connected to the second terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.