Marker layout method for optimizing overlay alignment in semiconductor device
US11215932B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jun 5, 2020 |
| Grant date | Jan 4, 2022 |
| Priority date | — |
| Expiry date | Jun 5, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F7/70683
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method of determining a marker layout for a semiconductor device includes determining the number of markers to be used in a field of a wafer using a first fitness function, calculating a marker probability distribution considering distance information among the markers and determining locations of a marker to be used according to the marker probability distribution, and evaluating performance of a final marker layout by using a second fitness function. The method provides an optimized approach to marker layout, so that the quality of a marker layout may be enhanced. Also, the method generates a marker layout that may minimize a prediction value of an overlay error of experimental wafers and an irregularity of marker locations, so that robust performance may be ensured for the prediction of overlay errors for subsequent new wafers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.