Double wrapping for verification
US11216562B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 31, 2019 |
| Grant date | Jan 4, 2022 |
| Priority date | — |
| Expiry date | Jul 10, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L9/3297
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and devices for double wrapping for verification are described. In some cases, a memory subsystem can receive a firmware image for the memory subsystem where the firmware image is signed with a first signature according to a first signing procedure. The memory subsystem can then verify an integrity of the firmware image based on the first signing procedure. After verifying the integrity of the firmware image, the memory subsystem can then generate a second signature for the firmware image based on a second signing procedure different from the first signing procedure. The memory subsystem can then write the second signature to the firmware image. The memory subsystem can then perform a verification process to verify the integrity of the firmware image based on one or both of the first signing procedure or the second signing procedure. In this case, a first verification time is associated with the first signing procedure and is greater than a second verification time associated with the second signing procedure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.