Methods for reducing transfer pattern defects in a semiconductor device

US11217448B2 · kind B2 · utility

Assignee

• Applied Materials, Inc. · US

Inventors

• Regina Freed · Los Altos, US
• Steven R. Sherman · Newton, US
• Nadine Alexis · Santa Clara, US
• Lin Zhou · Shijiazhuang, CN

Key dates

• Filing date: Jul 30, 2020
• Grant date: Jan 4, 2022
• Expiry date: Jul 30, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/31122
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Disclosed are methods for reducing transfer pattern defects in a semiconductor device. In some embodiments, a method includes providing a semiconductor device including a plurality of photoresist lines on a stack of layers, wherein the plurality of photoresist lines includes a bridge defect extending between two or more photoresist lines of the plurality of photoresist lines. The method may further include forming a plurality of mask lines by etching a set of trenches in a first layer of the stack of layers, and removing the bridge defect by etching the bridge defect at a non-zero angle of inclination with respect to a perpendicular to a plane of an upper surface of the stack of layers.