Method of forming a semiconductor device

US11217488B2 · kind B2 · utility

Assignee

• IMEC zvw · BE

Inventors

• Anabela Veloso · Leuven, BE
• Trong Huynh Bao · Leuven, BE
• Raf Appeltans · Haasrode, BE

Key dates

• Filing date: Mar 31, 2020
• Grant date: Jan 4, 2022
• Expiry date: Mar 31, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/85
• WIPO field: Micro-structural and nano-technology
• WIPO sector: Chemistry

Abstract

The disclosed technology generally relates to semiconductor devices and methods of forming the same. In one aspect, a method of forming a semiconductor device having vertical channel field-effect transistor (FET) devices comprises forming on a substrate, a plurality of semiconductor structures protruding vertically from a lower source/drain semiconductor layer of the substrate. The semiconductor structures can be arranged in an array having a plurality of rows and columns. The method can include etching metal line trenches between at least a subset of the rows and forming metal lines in the metal line trenches to contact the lower source/drain layer. The method can also include forming gate structures at least partly enclosing semiconductor structure channel portions located above the lower source/drain layer and forming upper source/drain metal contacts on semiconductor structure upper source/drain portions located above the channel portions.