Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same
US11217516B2 · kind B2 · utility
1Cited by
12References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2018 |
| Grant date | Jan 4, 2022 |
| Priority date | — |
| Expiry date | Dec 21, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stacked-chip apparatus includes a package substrate and an interposer with a chip stack disposed with a standoff that matches the interposer. A package-on-package stacked-chip apparatus includes a top package disposed on the interposer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.