Memory device and method for fabricating the memory device
US11217602B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 11, 2019 |
| Grant date | Jan 4, 2022 |
| Priority date | — |
| Expiry date | Apr 9, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/35
Abstract
Disclosed is a memory device and a method for fabricating the same, and the method may include forming an alternating stack in which dielectric layers and sacrificial layers are alternately stacked over a substrate, each of the sacrificial layers being a combination of porous and non-porous materials, forming a vertical opening penetrating the alternating stack, converting exposed surfaces of the sacrificial layers located on a side wall of the vertical opening into blocking layers through an oxidation process, forming a vertical channel structure contacting the blocking layers in the vertical opening, and replacing non-converting portions of the sacrificial layers with conductive layers, wherein each of the conductive layers comprises a round-like edge contacting each of the blocking layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.