Low clock load dynamic dual output latch circuit
US11218137B2 · kind B2 · utility
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24References
20Claims
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Key dates
| Filing date | Apr 14, 2020 |
| Grant date | Jan 4, 2022 |
| Priority date | — |
| Expiry date | May 1, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/20
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to integrated circuits, and more particularly, to a low clock load dynamic dual output latch circuit and methods of operation. The structure includes: a plurality of dynamic clocked stacks which are configured to receive input data and provide a true logical value and a complement logical value; and a plurality of holding stacks which are configured to provide a hold signal to the dynamic clocked stacks and output the true logical value and the complement logical value in response to the hold signal being activated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.