Inventor · Cupertino, CA, US

Mahbub Rashed

72Patents
11h-index
70Co-inventors
77Inventor score

Filing activity: Apr 1, 2005 → Oct 16, 2023

Most-cited inventions

PatentTitleAreaCited byStatus
US8741763B2 Layout designs with via routing structures Electricity 32 Active
US9337099B1 Special constructs for continuous non-uniform active region FinFET standard cells Electricity 31 Active
US7138842B2 Flip-flop circuit having low power data retention Electricity 22 Expired
US8987128B2 Cross-coupling based design using diffusion contact structures Emerging Cross-Sectional Technologies 19 Active
US8581348B2 Semiconductor device with transistor local interconnects Electricity 17 Active
US8881083B1 Methods for improving double patterning route efficiency Electricity 16 Active
US7274247B2 System, method and program product for well-bias set point adjustment Electricity 15 Expired
US9026977B2 Power rail layout for dense standard cell library Physics 14 Active
US8975712B2 Densely packed standard cells for integrated circuit products, and methods of making same Electricity 13 Active
US9196548B2 Methods of using a trench salicide routing layer Electricity 11 Active
US8618607B1 Semiconductor devices formed on a continuous active region with an isolating conductive structure positioned between such semiconductor devices, and methods of making same Electricity 11 Active
US8679911B2 Cross-coupling-based design using diffusion contact structures Electricity 10 Active
US9355910B2 Semiconductor device with transistor local interconnects Electricity 9 Active
US9035679B2 Standard cell connection for circuit routing Electricity 8 Active
US9006100B2 Middle-of-the-line constructs using diffusion contact structures Electricity 8 Active
US9122830B2 Wide pin for improved circuit routing Electricity 8 Active
US7542360B2 Programmable bias for a memory array Physics 7 Active
US9159724B2 Cross-coupling-based design using diffusion contact structures Electricity 6 Active
US8859416B2 Software and method for via spacing in a semiconductor device Electricity 5 Active
US8966423B2 Integrating optimal planar and three-dimensional semiconductor design layouts Physics 5 Active
US9519745B2 Method and apparatus for assisted metal routing Physics 5 Active
US9893063B2 Special construct for continuous non-uniform active region FinFET standard cells Electricity 5 Active
US8677291B1 Double patterning compatible colorless M1 route Electricity 5 Active
US10199378B2 Special construct for continuous non-uniform active region FinFET standard cells Electricity 5 Active
US10360334B2 Context aware processing to resolve strong spacing effects due to strain relaxation in standard cell library Physics 4 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.