Test and characterization of ring in superconducting domain through built-in self-test
US11218139B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 14, 2020 |
| Grant date | Jan 4, 2022 |
| Priority date | — |
| Expiry date | May 14, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1952
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Ring packet built-in self-test (PBIST) circuitry configured to detect errors in wires connecting a ring of superconducting chips includes circuitry configured to make the PBIST immune to interchip latency and still allow the PBIST to test a stop-to-stop connection. By making a PBIST independent of latency, an entire ring can be characterized for latency and for its bit-error rate prior to running any functional test. Such systems and associated methods can be scaled to larger platforms having any number of ring stops. The PBIST circuitry can function as either transmitter or receiver, or both, to test an entire ring. The PBIST can also be used to tune clocks in the ring to achieve the lowest overall bit error rate (BER) in the ring.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.