Combinatorial and sequential logic compaction in electronic circuit design emulation
US11221864B1 · kind B1 · utility
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20Claims
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Key dates
| Filing date | May 29, 2020 |
| Grant date | Jan 11, 2022 |
| Priority date | — |
| Expiry date | Jul 1, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/331
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An emulation host system can configure a reprogrammable hardware emulation system to emulate an electronic circuit design. The emulation host system can analyze the electronic circuit design for electronic circuits that are repetitive. The emulation host system can partition the electronic circuits onto a single partition. The emulation host system can map the single partition onto a single programmable logic element (PLE) of the reprogrammable hardware emulation system. The emulation host system can configure the reprogrammable hardware emulation system to emulate the electronic circuits using the single PLE.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.