Promotion of ERAT cache entries
US11221957B2 · kind B2 · utility
0Cited by
7References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2018 |
| Grant date | Jan 11, 2022 |
| Priority date | — |
| Expiry date | Sep 4, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/657
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, computer program product, and a computer system are disclosed for processing information in a processor that in one or more embodiments includes receiving a request for an Effective Address to Real Address Translation (ERAT); determining whether there is a permissions miss; changing, in response to determining there is a permission miss, permissions of an ERAT cache entry; and providing a Real Address translation. The method, computer program product, and computer system may optionally include providing a promote checkout request to a memory management unit (MMU).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.