Inventor · Byron, MN, US

Charles D. Wait

35Patents
7h-index
85Co-inventors
68Inventor score

Filing activity: May 26, 2005 → Aug 30, 2021

Most-cited inventions

PatentTitleAreaCited byStatus
US9081501B2 Multi-petascale highly efficient parallel supercomputer Emerging Cross-Sectional Technologies 85 Active
US7873816B2 Pre-loading context states by inactive hardware thread in advance of context switch Physics 36 Active
US9971713B2 Multi-petascale highly efficient parallel supercomputer Emerging Cross-Sectional Technologies 22 Active
US8291201B2 Dynamic merging of pipeline stages in an execution pipeline to reduce power consumption Emerging Cross-Sectional Technologies 13 Active
US8930432B2 Floating point execution unit with fixed point functionality Physics 10 Active
US8412760B2 Dynamic range adjusting floating point execution unit Physics 8 Active
US8140830B2 Structural power reduction in multithreaded processor Emerging Cross-Sectional Technologies 8 Active
US7296108B2 Apparatus and method for efficient transmission of unaligned data Physics 6 Expired
US9223753B2 Dynamic range adjusting floating point execution unit Physics 5 Active
US8707094B2 Fault tolerant stability critical execution checking using redundant execution pipelines Physics 5 Active
US10318435B2 Ensuring forward progress for nested translations in a memory management unit Physics 5 Active
US8412980B2 Fault tolerant stability critical execution checking using redundant execution pipelines Physics 4 Active
US7814299B2 Designating operands with fewer bits in instruction code by indexing into destination register history table for each thread Physics 4 Active
US7975172B2 Redundant execution of instructions in multistage execution pipeline during unused execution cycles Physics 4 Active
US8880852B2 Detecting logically non-significant operation based on opcode and operand and setting flag to decode address specified in subsequent instruction as different address Physics 3 Active
US9395804B2 Branch prediction with power usage prediction and control Emerging Cross-Sectional Technologies 3 Active
US9195463B2 Processing core with speculative register preprocessing in unused execution unit cycles Physics 3 Active
US8255674B2 Implied storage operation decode using redundant target address detection Physics 3 Active
US10067556B2 Branch prediction with power usage prediction and control Emerging Cross-Sectional Technologies 3 Active
US10042417B2 Branch prediction with power usage prediction and control Emerging Cross-Sectional Technologies 3 Active
US8028153B2 Data dependent instruction decode Physics 3 Active
US8629867B2 Performing vector multiplication Physics 2 Active
US8560924B2 Register file soft error recovery Physics 1 Active
US8522254B2 Programmable integrated processor blocks Physics 1 Active
US11422947B2 Determining page size via page table cache Physics 1 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.