State table complexity reduction in a hierarchical verification flow
US11222154B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 5, 2020 |
| Grant date | Jan 11, 2022 |
| Priority date | — |
| Expiry date | Oct 5, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
State table complexity reduction in a hierarchical verification flow is provided by identifying peripheral supplies and non-peripheral supplies in a hierarchical group in a hierarchical logical block model of a circuit based on whether logic blocks associated with the power supplies provide outputs to or receive inputs from circuity external to the hierarchical group; merging associated power state tables for the peripheral supplies and the non-peripheral supplies in the hierarchical group to create a merged power state table for the hierarchical group; removing, by a processing device, any power states associated with the non-peripheral supplies from the merged power state table to create a reduced power state table; and modeling a reduced logical block based on the reduced power state table.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.