Load balancing for memory channel controllers
US11222258B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 4, 2020 |
| Grant date | Jan 11, 2022 |
| Priority date | — |
| Expiry date | May 4, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/5016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and apparatus, including computer-readable media, are described for performing neural network computations using a system configured to implement a neural network on a hardware circuit. The system includes a process ID unit that receives requests to obtain data from a memory that includes memory locations that are each identified by an address. For each request, the process ID unit selects a channel controller to receive the request, provides the request to be processed by the selected channel controller, and obtains the data from memory in response to processing the request using the selected channel controller. The channel controller is one of multiple channel controllers that are configured to access any memory location of the memory. The system performs the neural network computations using the data obtained from memory and resources allocated from a shared memory of the hardware circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.