Refresh management for DRAM
US11222685B2 · kind B2 · utility
2Cited by
2References
33Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 15, 2020 |
| Grant date | Jan 11, 2022 |
| Priority date | — |
| Expiry date | May 15, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/40618
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller interfaces with a dynamic random access memory (DRAM) over a memory channel. A refresh control circuit monitors an activate counter which counts a rolling number of activate commands sent over the memory channel to a memory region of the DRAM. In response to the activate counter being above an intermediate management threshold value, the refresh control circuit only issue a refresh management (RFM) command if there is no REF command currently held at the refresh command circuit for the memory region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.