Source/drain diffusion barrier for germanium NMOS transistors

US11222977B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Glenn A. Glass · Portland, US
• Anand S. Murthy · Beaverton, US
• Karthik Jambunathan · Hillsboro, US
• Cory Bomberger · Portland, US
• Tahir Ghani · Portland, US
• Jack T. Kavalieros · Portland, US
• Benjamin Chu-Kung · Portland, US
• Seung Hoon Sung · Beaverton, US
• Siddharth Chouksey · Portland, US

Key dates

• Filing date: Sep 26, 2017
• Grant date: Jan 11, 2022
• Expiry date: Sep 26, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/017

Abstract

Integrated circuit transistor structures are disclosed that reduce n-type dopant diffusion, such as phosphorous or arsenic, from the source region and the drain region of a germanium n-MOS device into adjacent shallow trench isolation (STI) regions during fabrication. The n-MOS transistor device may include at least 75% germanium by atomic percentage. In an example embodiment, the structure includes an intervening diffusion barrier deposited between the n-MOS transistor and the STI region to provide dopant diffusion reduction. In some embodiments, the diffusion barrier may include silicon dioxide with carbon concentrations between 5 and 50% by atomic percentage. In some embodiments, the diffusion barrier may be deposited using chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) techniques to achieve a diffusion barrier thickness in the range of 1 to 5 nanometers.