Scalable matrix node engine with configurable data formats
US11227029B2 · kind B2 · utility
1Cited by
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15Claims
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Key dates
| Filing date | May 23, 2019 |
| Grant date | Jan 18, 2022 |
| Priority date | — |
| Expiry date | May 23, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/4824
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor system comprises a matrix computational unit and a control unit. The matrix computational unit includes one or more processing elements. The control unit is configured to provide a matrix processor instruction to the matrix computational unit. The matrix processor instruction specifies a floating-point operand formatted with an exponent that has been biased with a specified bias.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.