Memory device and operating method thereof
US11227660B2 · kind B2 · utility
2Cited by
10References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 10, 2020 |
| Grant date | Jan 18, 2022 |
| Priority date | — |
| Expiry date | Sep 10, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/32
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a cell array and a page buffer circuit. The cell array includes a first to fourth cell strings respectively connected to a first to fourth bit lines. The page buffer circuit is configured to apply an erase voltage to the first and third bit lines based on a first control signal during an erase operation for memory cells of the first to fourth cell strings. The page buffer circuit is configured to place the second and fourth bit lines in a floating state based on a second control signal during the erase operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.