Method for making self-aligned barrier for metal vias In-Situ during a metal halide pre-clean and associated interconnect structure
US11227794B2 · kind B2 · utility
2Cited by
11References
20Claims
0Family size
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Key dates
| Filing date | Dec 19, 2019 |
| Grant date | Jan 18, 2022 |
| Priority date | — |
| Expiry date | Mar 31, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multi-layer interconnect structure with a self-aligning barrier structure and a method for fabricating the same is disclosed. For example, the method includes forming a via through an interlayer dielectric (ILD) layer, an etch stop layer (ESL), and a contact structure, pre-cleaning the via with a metal halide, forming a barrier structure on the contact structure in-situ during the pre-cleaning of the via with the metal halide, and depositing a second metal in the via on top of the barrier structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.