Multi-chip package power module
US11227856B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 7, 2020 |
| Grant date | Jan 18, 2022 |
| Priority date | — |
| Expiry date | Jan 7, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/04105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multi-chip package power module according to the present disclosure, comprising: multiple chips, including a first chip and a second chip that are arranged adjacently; a first conductive member, at least partially arranged between the first chip and the second chip, and a second conductive member, at least partially arranged between the first chip and the second chip, where the first conductive member is electrically connected to a power pin of the first chip, the second conductive member is electrically connected to a power pin of the second chip, and the multiple chips, the first conductive member and the second conductive member are all embedded in an insulating package material. For the multi-chip package power module according to the present disclosure, the power output current of the chip can be directly led out from two opposite sides through the conductive member to obtain a symmetrical path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.