Stacked package with electrical connections created using high throughput additive manufacturing
US11227859B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2017 |
| Grant date | Jan 18, 2022 |
| Priority date | — |
| Expiry date | Oct 15, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/1094
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A device package and a method of forming the device package are described. The device package includes one or more dies disposed on a first substrate. The device packages further includes one or more interconnects vertically disposed on the first substrate, and a mold layer disposed over and around the first die, the one or more interconnects, and the first substrate. The device package has a second die disposed on a second substrate, wherein the first substrate is electrically coupled to the second substrate with the one or more interconnects, and wherein the one or more interconnects are directly disposed on at least one of a top surface of the first substrate and a bottom surface of the second substrate without an adhesive layer. The device package may include one or more interconnects having one or more different thicknesses or heights at different locations on the first substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.