MRAM integration with BEOL interconnect including top via

US11227892B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Ashim Dutta · Clifton Park, US
• Chih-Chao Yang · Glenmont, US
• Ekmini Anuja De Silva · Slingerlands, US
• Dominik Metzler · Clifton Park, US

Key dates

• Filing date: Jun 18, 2019
• Grant date: Jan 18, 2022
• Expiry date: Jul 1, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10N50/80

Abstract

A method is presented for preventing excessive cap dielectric loss in memory areas and logic areas of a device. The method includes forming a first conductive line with top via and a conductive pad over a dielectric layer, wherein the conductive pad includes a microstud, depositing a dielectric cap in direct contact with the first conductive line and the conductive pad, and constructing a top electrode, a magnetic tunnel junction (MTJ) stack, and a bottom electrode in vertical alignment with the microstud of the conductive pad.