Augmenting an integrated circuit (IC) design simulation model to improve performance during verification
US11231462B1 · kind B1 · utility
1Cited by
11References
19Claims
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Key dates
| Filing date | Jun 25, 2020 |
| Grant date | Jan 25, 2022 |
| Priority date | — |
| Expiry date | Jun 25, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/333
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An augmented simulation model can be created of an integrated circuit (IC) design by inserting a switch in a simulation model of the IC design between an output of a scan cell and an input of a combinational logic cloud. A simulation enable signal can be used to control the switch. Next, an IC design simulation environment can be generated based on the augmented simulation model. The IC design can be verified by using the IC design simulation environment. The simulation enable signal can be activated when the combinational logic cloud is desired to be simulated by the IC design simulation environment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.