Error-checking in namespaces on storage devices
US11232028B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 15, 2020 |
| Grant date | Jan 25, 2022 |
| Priority date | — |
| Expiry date | May 15, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7201
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods for storing and validating namespace metadata are disclosed. An exemplary system includes a memory component and a processing device receiving a first read instruction from a host process. The first read instruction includes a namespace offset. A first logical address is generated by combining a namespace identifier for the namespace assigned to the host process and the namespace offset. The first logical address is translated into a first physical address using a plurality of hierarchical tables. A second read instruction, which includes the first physical address and the first logical address, is generated. The second read instruction is sent to a memory component. The memory component validates the translation of the first logical address by comparing the first logical address in the second read instruction to metadata associated with data to be read at the first physical address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.