Layout-friendly test pattern decompressor
US11232246B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 28, 2020 |
| Grant date | Jan 25, 2022 |
| Priority date | — |
| Expiry date | Oct 28, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit comprises: a register configured to be a linear finite state machine and comprising storage elements, injection devices, one or more input channels for injecting variables using the injection devices, and one or more feedback devices; a plurality of phase shifters, each of the plurality of phase shifters configured to receive signals from a unique segment of the register; scan chains, serial inputs of the scan chains configured to receive signals from outputs of the plurality of phase shifters, wherein the one or more input channels are coupled to the injection devices at injection points in the register, each of the injection points being assigned to one of the one or more input channels based on lifespan values for the injection points, the injection points being determined based on one or more predetermined requirements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.