Mark Kassab
59Patents
20h-index
28Co-inventors
88Inventor score
Filing activity: Jun 11, 1993 → May 26, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6557129B1 | Method and apparatus for selectively compacting test responses | Physics | 136 | Expired |
| US6327687A | Test pattern compression for an integrated circuit test environment | Physics | 128 | Expired |
| US6684358B1 | Decompressor/PRPG for applying pseudo-random and deterministic test patterns | Physics | 113 | Expired |
| US6829740B2 | Method and apparatus for selectively compacting test responses | Physics | 86 | Expired |
| US6543020B2 | Test pattern compression for an integrated circuit test environment | Physics | 86 | Expired |
| US7093175B2 | Decompressor/PRPG for applying pseudo-random and deterministic test patterns | Physics | 62 | Expired |
| US6353842B1 | Method for synthesizing linear finite state machines | Physics | 61 | Expired |
| US7111209B2 | Test pattern compression for an integrated circuit test environment | Physics | 59 | Expired |
| US7818644B2 | Multi-stage test response compactors | Physics | 50 | Active |
| US6708192B2 | Method for synthesizing linear finite state machines | Physics | 48 | Expired |
| US6539409B2 | Method for synthesizing linear finite state machines | Physics | 46 | Expired |
| US7500163B2 | Method and apparatus for selectively compacting test responses | Physics | 41 | Expired |
| US7260591B2 | Method for synthesizing linear finite state machines | Physics | 33 | Expired |
| US7493540B1 | Continuous application and decompression of test patterns to a circuit-under-test | Physics | 31 | Expired |
| US7506232B2 | Decompressor/PRPG for applying pseudo-random and deterministic test patterns | Physics | 31 | Active |
| US7925465B2 | Low power scan testing techniques and apparatus | Physics | 29 | Active |
| US7509546B2 | Test pattern compression for an integrated circuit test environment | Physics | 28 | Active |
| US7478296B2 | Continuous application and decompression of test patterns to a circuit-under-test | Physics | 28 | Expired |
| US7805649B2 | Method and apparatus for selectively compacting test responses | Physics | 21 | Active |
| US8726112B2 | Scan test application through high-speed serial input/outputs | Physics | 20 | Active |
| US7555689B2 | Generating responses to patterns stimulating an electronic circuit with timing exception paths | Physics | 18 | Active |
| US7900104B2 | Test pattern compression for an integrated circuit test environment | Physics | 12 | Active |
| US7877656B2 | Continuous application and decompression of test patterns to a circuit-under-test | Physics | 11 | Active |
| US8290738B2 | Low power scan testing techniques and apparatus | Physics | 10 | Active |
| US7865794B2 | Decompressor/PRPG for applying pseudo-random and deterministic test patterns | Physics | 10 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.