Erasing method for 3D NAND flash memory
US11232839B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 2, 2020 |
| Grant date | Jan 25, 2022 |
| Priority date | — |
| Expiry date | Oct 2, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/27
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of erasing methods for a three-dimensional (3D) memory device are disclosed. The 3D memory device includes multiple decks vertically stacked over a substrate, wherein each deck includes a plurality of memory cells. The erasing method includes checking states of the plurality of memory cells of an erase-inhibit deck and preparing the erase-inhibit deck according to the states of the plurality of memory cells. The erasing method also includes applying an erase voltage at an array common source, applying a hold-release voltage on unselected word lines of the erase-inhibit deck, and applying a low voltage on selected word lines of a target deck.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.