Methods and devices for testing multiple memory configurations
US11232847B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 20, 2019 |
| Grant date | Jan 25, 2022 |
| Priority date | — |
| Expiry date | Sep 20, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/2602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, devices, and systems for testing a number of combinations of memory in a computer system. A modular memory device is installed in a memory channel in communication with a processor. The modular memory device includes a number of memory storage devices. The number of memory storage devices include a number of pins. A subset of the number of memory storage devices is selected. A subset of the plurality of pins which do not correspond to the subset of the number of memory storage devices and are not part of a memory map of the computer system is selected. Each pin of the subset of the plurality of pins configured with a termination impedance. The subset of the number of memory storage devices is tested.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.