Method for preparing semiconductor device with composite landing pad
US11232984B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 14, 2020 |
| Grant date | Jan 25, 2022 |
| Priority date | — |
| Expiry date | Sep 14, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a method for preparing a semiconductor device with a composite landing pad. The method includes forming a first dielectric layer over a semiconductor substrate. The method also includes forming a barrier layer and a first lower metal plug penetrating through the first dielectric layer and in a cell region. The first lower metal plug is surrounded by the barrier layer. The method further includes depositing a silicon layer over the first dielectric layer, the barrier layer and the first lower metal plug. In addition, the method includes performing a salicide process to form an inner silicide portion over the first lower metal plug and an outer silicide portion over the barrier layer after the silicon layer is formed. The inner silicide portion is surrounded by the outer silicide portion, and a recess is formed over the inner silicide portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.