Integrated circuit devices including enlarged via and fully aligned metal wire and methods of forming the same
US11232986B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 10, 2020 |
| Grant date | Jan 25, 2022 |
| Priority date | — |
| Expiry date | Feb 10, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76883
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Integrated circuit devices and methods of forming the same are provided. The methods of forming an integrated circuit device may include forming a first insulating layer and a via contact on a substrate. The substrate may include an upper surface facing the via contact, and the via contact may be in the first insulating layer and may include a lower surface facing the substrate and an upper surface opposite to the lower surface. The methods may also include forming a second insulating layer and a metallic wire on the via contact. The metallic wire may be in the second insulating layer and may include a lower surface that faces the substrate and contacts the upper surface of the via contact. Both the lower surface of the metallic wire and an interface between the metallic wire and the via contact may have a first width in a horizontal direction that is parallel to the upper surface of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.